Overview
There’s growing concern that transient problems, brought on by cosmic sun rays along with other factors, will occur frequently later on high-performance processors, as designers push technology to the extreme limits. Existing fault-tolerant techniques are generally too pricey (system-level replication), too intrusive (gate-level replication), or too specific (e.g. ECC on memory). In 1999, we suggested a microarchitectural method of fault tolerance (AR-SMT), achieving broad coverage of transient problems with low performance overhead and couple of changes towards the underlying microarchitecture. We revisit this notion and explore different ways the microarchitecture might help reliability.
This project is continuing. For background, please stick to the Slipstream Project link around the primary research page.
Publications
VKay. Reddy and E. Rotenberg. Coverage of the Microarchitecture-level Fault Check Regimen inside a Superscalar Processor. Proceedings from the 38th IEEE/IFIP Worldwide Conference on Dependable Systems and Systems (DSN-38, DCCS track). pp. 1-10, June 2008. [pdf ]
VKay. Reddy and E. Rotenberg. Natural Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. Proceedings from the 37th IEEE/IFIP Worldwide Conference on Dependable Systems and Systems (DSN-37, DCCS track). pp. 307-316, June 2007. [pdf ]
VKay. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding Conjecture-Based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance. Proceedings from the twelfth ACM Worldwide Conference on Architectural Support for Programming Languages and Os’s (ASPLOS-XII). pp. 83-94, October 2006. [pdf ]
VKay. Reddy, A.
S. Al-Zawawi, and E. Rotenberg. Assertion-Based Microarchitecture The perception of Improved Fault Tolerance. Proceedings from the 24th IEEE Worldwide Conference on Computer Design (ICCD-24). pp. 362-369, October 2006. [pdf ]
S. Rajan Vijaya Kumar. RTL Design and Analysis of the Fault Check Regimen for Superscalar Processors. M.S. Thesis, Department of Electrical and Computer Engineering, New York Condition College, This summer 2010. [NCSU library: on-line thesis ]
VKay. Reddy. Exploiting Microarchitecture Insights for Efficient Fault Tolerance. Ph.D. Thesis, Department of Electrical and Computer Engineering, New York Condition College, August 2007. [NCSU library: on-line thesis ]
S. Parthasarathy. Improving Transient Fault Tolerance of Slipstream Processors. M.S. Thesis, Department of Electrical and Computer Engineering, New York Condition College, December 2005. [NCSU library: on-line thesis ]
Talks
Coverage of the Microarchitecture-level Fault Check Regimen inside a Superscalar Processor. Presented at DSN-38 by VKay. Reddy. [pps]
Natural Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. Presented at DSN-37 by VKay. Reddy. [pps ]
Understanding Conjecture-Based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance. Presented at ASPLOS-12 by VKay. Reddy. [pps ]
Assertion-Based Microarchitecture The perception of Improved Fault Tolerance. Presented at ICCD-24 by VKay. Reddy. [pps ]
Funding
This project is based on NSF CAREER grant No.
CCR-0092832 (CAREER: Cooperative Redundant Threads ), and generous funding and equipment donations from Apple.
Any opinions, findings, and conclusions or recommendations expressed within this website and publications herein are individuals from the author(s) and don’t always reflect the views from the National Science Foundation.
Overview
There’s growing concern that transient problems, brought on by cosmic sun rays along with other factors, will occur frequently later on high-performance processors, as designers push technology to the extreme limits. Existing fault-tolerant techniques are generally too pricey (system-level replication), too intrusive (gate-level replication), or too specific (e.g. ECC on memory). In 1999, we suggested a microarchitectural method of fault tolerance (AR-SMT), achieving broad coverage of transient problems with low performance overhead and couple of changes towards the underlying microarchitecture. We revisit this notion and explore different ways the microarchitecture might help reliability.
This project is continuing. For background, please stick to the Slipstream Project link around the primary research page.
Publications
VKay. Reddy and E. Rotenberg. Coverage of the Microarchitecture-level Fault Check Regimen inside a Superscalar Processor. Proceedings from the 38th IEEE/IFIP Worldwide Conference on Dependable Systems and Systems (DSN-38, DCCS track). pp. 1-10, June 2008. [pdf ]
VKay. Reddy and E. Rotenberg. Natural Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. Proceedings from the 37th IEEE/IFIP Worldwide Conference on Dependable Systems and Systems (DSN-37, DCCS track). pp. 307-316, June 2007. [pdf ]
VKay. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding Conjecture-Based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance. Proceedings from the twelfth ACM Worldwide Conference on Architectural Support for Programming Languages and Os’s (ASPLOS-XII). pp. 83-94, October 2006. [pdf ]
VKay. Reddy, A. S. Al-Zawawi, and E. Rotenberg. Assertion-Based Microarchitecture The perception of Improved Fault Tolerance. Proceedings from the 24th IEEE Worldwide Conference on Computer Design (ICCD-24). pp. 362-369, October 2006. [pdf ]
S. Rajan Vijaya Kumar. RTL Design and Analysis of the Fault Check Regimen for Superscalar Processors. M.S. Thesis, Department of Electrical and Computer Engineering, New York Condition College, This summer 2010. [NCSU library: on-line thesis ]
VKay. Reddy. Exploiting Microarchitecture Insights for Efficient Fault Tolerance. Ph.D. Thesis, Department of Electrical and Computer Engineering, New York Condition College, August 2007. [NCSU library: on-line thesis ]
S. Parthasarathy. Improving Transient Fault Tolerance of Slipstream Processors. M.S. Thesis, Department of Electrical and Computer Engineering, New York Condition College, December 2005. [NCSU library: on-line thesis ]
Talks
Coverage of the Microarchitecture-level Fault Check Regimen inside a Superscalar Processor. Presented at DSN-38 by VKay. Reddy. [pps]
Natural Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. Presented at DSN-37 by VKay. Reddy. [pps ]
Understanding Conjecture-Based Partial Redundant Threading for Low-Overhead, High-Coverage Fault Tolerance. Presented at ASPLOS-12 by VKay. Reddy. [pps ]
Assertion-Based Microarchitecture The perception of Improved Fault Tolerance. Presented at ICCD-24 by VKay. Reddy. [pps ]
Funding
This project is based on NSF CAREER grant No. CCR-0092832 (CAREER: Cooperative Redundant Threads ), and generous funding and equipment donations from Apple.
Any opinions, findings, and conclusions or recommendations expressed within this website and publications herein are individuals from the author(s) and don’t always reflect the views from the National Science Foundation.
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