Electrical Engineering Paper
For a 64-bit CPU design an adder circuit is considered as one of the key building blocks. Students are required to create spice simulation of a 1-bit half adder circuit using CMOS logic, transmission gate, and dynamic logic. (30 points) a) Based on the sizing of the transistor predict the most area efficient design among CMOS logic, transmission gate and dynamic logic based 1-bit half adder. (Answer briefly- no more than three sentences). (30 points) b) If the (W/L) of transistors at gate level kept same for 1-bit half adder in CMOS logic, transmission gate and dynamic logic, which one will be fastest in driving same amount of load. (Answer briefly- no more than three sentences). (30 points) c) Pick the most power efficient among the three choices. (Answer briefly- no more than three sentences). (30 points)
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